Nvidia Recruitment 2025
NVIDIA Off Campus Drive 2025
Nvidia is looking for talented individuals to innovate in graphics technology. As a global leader in the industry, they value creativity and drive. Join Nvidia to help shape the future of AI, gaming, and automotive technology. Be a part of a dynamic team that is pushing the boundaries of visual computing. If you’re passionate about cutting-edge innovation, Nvidia offers an exciting platform for your career growth.
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1. System Software Engineer, DGX Spark (2+ yrs)
Nvidia is hiring for the post of System Software Engineer, DGX Spark. Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bengaluru/ Pune, India
Position : System Software Engineer, DGX Spark
Education : B.E./ B.Tech /M.Tech
Experience : 2+ years
Req Id : JR1998979
NVIDIA Recruitment 2025
Join us at NVIDIA as a System Software Engineer in Bangalore, and collaborate on brand new embedded computing and artificial intelligence technologies developed around the NVIDIA Platform for AI. Visit us here https://www.nvidia.com/en-in/products/workstations/dgx-spark/ to know more. This is your opportunity to be part of a team that is revolutionizing the future of computing with our AI Supercomputer!
What you’ll be doing:
√ NVIDIA SoC and Board support, including interprocessor communications, CPU architecture, memory management, power, and clock design.
√ Developing and integrating drivers for I/O bus interfaces such as PCIe, I2C, SPI, CAN, GPIO, Wifi, USB3.x, FDI storage, NVME, QSPI, Ethernet.
√ Board Bring-ups and Collaborating with vendors and suppliers to integrate solutions seamlessly.
√ Engaging with the Linux and open-source software communities, working across multiple Linux distributions and processor architectures.
√ Applying GNU GCC Toolchain & Makefiles.
√ Managing bootloaders and complete system boot processes.
What we need to see:
√ B.E/ B.Tech/ MS/ M.Tech or PhD in Electronics/ Computer Science Engineering.
√ 2+ years of software development experience with a strong emphasis on Linux kernel development.
√ Proven C programming and debugging skills.
√ Familiarity with ARM Architecture.
√ Ability to work effectively in a multi-national, multi-time-zone environment.
√ Deep understanding of computer system architecture and operating systems.
√ Experience with real-time or soft real-time OS and application programming.
√ Dedicated with demonstrated experience bringing a new product to market.
√ Basic scripting knowledge in languages such as Python, Perl, Shell.
√ Excellent communication skills, both verbal and written, and a great teammate.
How to Apply :
All interested and eligible candidates can apply in online mode for System Software Engineer, DGX Spark position….👇👇
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System Software Engineer Salary : 💵💵The salary for this role is upto ₹26.5 LPA *💵💵
2. Mask Designer (2+ yrs)
Nvidia is hiring for the post of Mask Designer. Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bengaluru, KA, India
Position : Mask Designer
Education : B.E./ B.Tech /M.Tech
Experience : 2+ years
Req Id : JR1997059
NVIDIA Recruitment 2025
We are looking for a Digital/Memory Mask Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.
NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
What you’ll be doing:
» Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.
» Lead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.
» Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.
» Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.
» Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.
» Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.
» Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.
» Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.
» Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.
» Excel in resource management, representing the team in technical discussions with customers
» IP layout will comprise of significant digital components.
» Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts
» Follow company procedures and practices for IC layout activities.
What we need to see:
» B.E/ B.Tech./ M.Tech in Electronics or equivalent experience with 2+ years of proven experience in Memory layout in advanced CMOS process.
» Detailed knowledge of industry standard EDA tools for Cadence.
» Experience with layout of high-performance memories of various types.
» Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)
» Experience with floor planning, block level routing and macro level assembly.
» Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.
How to Apply :
All interested and eligible candidates can apply in online mode for Mask Designer position….👇👇
Join our Telegram group: Click here
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Join our WhatsApp group: Click here
Mask Designer Salary : 💵💵The salary for this role is upto ₹ 38.00 LPA *💵💵
3. ASIC Engineer (2+ yrs)
Nvidia is hiring for the post of ASIC Engineer. Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bengaluru, KA, India
Position : ASIC Engineer
Education : B.Tech /M.Tech
Experience : 2+ years
Req Id : JR1978791
NVIDIA Recruitment 2025
We are now looking for highly driven and innovative ASIC / Hardware Engineers. We are looking for bright engineers across our hardware engineering groups to help us Architect, Design and verify our next generation GPUs, CPU and SoCs meant to accelerate the performance of Data Center, Machine Learning, Autonomous Driving, Ray Tracing and many more exciting applications. You will get to work on high performance GPU / SOC/ CPU across Memory sub-systems, Graphic processing units, NOC based Interconnect Fabric, High speed IO’s etc.
What you’ll be doing:
» Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system.
» Work closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption.
» Understand key performance use cases or the product. Develop workloads and test suites targeting graphics, machine learning, automotive, video, compute vision applications running on our products.
» You will be responsible to make architectural trade-offs based on feature/performance/power requirements, analyse system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation.
» Developing test plans, tests and verification infrastructure for complex IP’s/sub-system/SOC’s.
» Creating verification environment using UVM methodology and reusable bus functional models, monitors, checkers and scoreboards.
» Driving functional coverage driven verification closure.
» Develop and enhance timing analysis/signoff work-flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
» Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
» Chip level Integration, physically partitioning and floor planning along with Physical Verification and EM IR Drop
» You will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
» In addition, you will help develop and deploy DFT methodologies for our next generation products.
» Be apart of innovation to strive improve the quality of DFT methods.
» Work with architects, designers and post-silicon teams.
What we need to see:
» B.Tech /M.Tech with 2+ years of experience in micro-architecture, RTL development of complex designs.
» Possess strong digital design fundamentals.
» Preferably have a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor planning, ECO, bring up and lab debug is a prerequisite for this role.
» If you have experience in at least a few of the following skills, we will have an excellent match for our needs:
» GPU / CPU / SOC Performance verification and analysis.
» CPU, Memory controller, Bus Interconnect, Cache coherency
» IP / SOC Design, Micro-architecture across High Speed IO controller (UFS/PCIE/ XUSB), Network on Chip / 10G Ethernet MAC and (or) Switch
» Graphics Processing Unit (GPU Design & Verification)
» BOOT and Power management features for complex SOC’s
» FPGA Prototype with prior experience in HAP
» Good debugging and analytical skills.
» Good interpersonal skills and ability to work as an excellent teammate
» Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization
How to Apply :
All interested and eligible candidates can apply in online mode for ASIC Engineer position….👇👇
Join our Telegram group: Click here
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ASIC Engineer Salary : 💵💵The salary for this role is upto ₹ 24.00 LPA *💵💵
4. DFT Engineer – Hardware (2+ yrs)
NVIDIA is hiring for the post of DFT Engineer – Hardware for Bangalore locations. Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bangalore, India
Position : DFT Engineer – Hardware
Education : Bachelor’s / Master’s degree
Experience : 2+ years
Req Id : JR1993651
NVIDIA Recruitment 2025
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. Make the choice to join us today. NVIDIA is an equal opportunity employer. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry’s most complex semiconductor chips. We are looking for a DFT Engineer.
What you’ll be doing:
» As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
» Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
» In addition, you will help develop and deploy DFT methodologies for our next generation products.
» Be apart of innovation to strive improve the quality of DFT methods.
» You will also need to work with multi-functional teams to incorporate DFT features into the chip.
» Occasional travel and also some late hours online meetings involved during critical milestones.
What we need to see:
» BS in EE or MS in EE from reputed institutions or equivalent experience with 2+ years of experience
» You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
» Experience in RTL and Gates verification and simulation.
» You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
» Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
» Strong analytical and problem solving skills with good scripting knowledge (either Perl / Python)
How to Apply :
All interested and eligible candidates can apply in online mode for DFT Engineer – Hardware position…..👇👇
Join our Telegram group: Click here
Follow us on Instagram: Click here
Join our WhatsApp group: Click here
DFT Engineer Salary : 💵💵The salary for this role is upto ₹28.70 LPA *💵💵
#. SOC Design Engineer (2+ yrs)
Sorry, this position has been filled.
NVIDIA is hiring for the post of SOC Design Engineer for Bangalore locations. Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bangalore, India
Position : SOC Design Engineer
Education : Bachelor’s / Master’s degree
Experience : 2+ years
Req Id : JR1994632
NVIDIA Recruitment 2025
NVIDIA System-On-Chip (SOC) group is hiring for an SOC Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a star candidate with strong inclination in RTL integration and chip level front-end design, including padring, pinmuxing, SOC Assembly process, retiming etc. You must have a real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the chance to build sophisticated Tegra SOCs, work closely with chip management to set ASIC execution timelines & goals while directly interacting with System Architecture, unit-level ASIC, Physical Design, CAD, Package Design, DFT and other teams. Additionally, you will be involved in defining and crafting methodologies that build more efficient and flexible SOCs in future.
What you’ll be doing:
〉 Drive SOC Assembly and design chip level functions for Tegra SOCs.
〉 Responsible for front-end design quality/correctness checks, reviews and driving those with multi-functional teams.
〉 Drive SOC execution across chip milestones working with all multi-functional teams to help define, track and drive complex dependencies.
〉 Define and develop system-level methodologies, tools, and IPs to build SOCs in an efficient and scalable manner.
〉 Identify difficulties and inefficiencies in the front-end chip implementation process and propose and implement ideas to solve them.
What we need to see:
〉 B.Tech or M.Tech in Electronics Engineering.
〉 2+ years of proven experience in chip design, specializing in SOC integration and design automation. Padring and fuse/floorsweep design experience is a bonus.
〉 Excellent analytical and problem-solving skills.
〉 Experience in RTL design (Verilog), System-On-Chip design/implementation flow.
〉 Strong coding skills in Perl, Python, or other industry-standard scripting languages.
〉 Exposure to various Chip Design Functions to be able to collaborate and solve complex multi-functional problems.
〉 Excellent interpersonal skills to work with multiple teams to drive consensus.
〉 Good teamwork spirit and collaboration skills with team members.
〉 Background in SOC Verification, Synthesis, Physical design and DFT is a bonus.
〉 Experience in RTL Build flows and Makefiles is a plus.
How to Apply :
All interested and eligible candidates can apply in online mode for SOC Design Engineer position. 👇👇
Join our Telegram group: Click here
Follow us on Instagram: Click here
Join our WhatsApp group: Click here
SOC Design Engineer Salary : 💵💵The salary for this role is upto ₹ 44.00 LPA *💵💵
#. ASIC Engineer- PCIE (2+ yrs)
Sorry, this position has been filled.
Nvidia is hiring for the post of ASIC Engineer – PCIE. Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bengaluru, KA, India
Position : ASIC Engineer – PCIE
Education : BS / MS
Experience : 2+ years
Req Id : JR1981358
NVIDIA Recruitment 2025
NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for the world’s leading SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.”
What you’ll be doing:
» Own the micro-architecture and RTL development of design modules for PCI Express Controllers.
» Micro-architect features to meet performance, power and area requirements.
» Work with HW and system architects to define critical features.
» Help verification teams to verify the correctness of implemented features.
» Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.
» Enable FPGA and software teams to prototype the design and ensure that software is tested.
» Work on post-silicon verification and debug.
What we need to see:
» BS / MS or equivalent experience.
» 2+ years of design experience.
» Experience in micro-architecture and RTL design of complex units.
» Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, Verdi).
» Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
» Expertise in Verilog.
» Ways to stand out from the crowd:
» Design experience in High Speed IO controllers like PCI Express.
» Good knowledge of PCI Express Protocol – Gen 3 and above.
» Good debugging and problem solving skills.
» Scripting knowledge (Python/Perl/shell).
» Good interpersonal skills and ability & desire to work as a teammate.
How to Apply :
All interested and eligible candidates can apply in online mode for Data Engineer – PCIE position.
Join our Telegram group: Click here
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Join our WhatsApp group: Click here
Data Engineer Salary : The salary for this role is upto ₹ 28.00 LPA *
#. ASIC Design Engineer (2+ yrs)
Sorry, this position has been filled.
Nvidia is hiring for the post of ASIC Design Engineer . Interested and eligible candidates can read more details below.
Company Name : Nvidia
Job Location : Bengaluru, KA, India
Position : ASIC Design Engineer
Education : BS / MS
Experience : 2+ years
Req Id : JR1981954
NVIDIA Recruitment 2025
NVIDIA is seeking outstanding ASIC Design Engineers to design and implement world’s leading SoC’s. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is encouraged to do their best work. Come join the team and see how you can make a lasting impact on the world.
What you will be doing:
» Partner with system architects to understand the functional and performance requirements of a unit or feature
» Define micro-architecture and develop RTL for owned unit and/or feature
» Work with verification and physical design team to ensure that the unit or feature is accurately verified and implemented
» You will own silicon bring-up in conjunction with post silicon validation and SW teams
» Mentor junior engineers and guide them in their work
What we need to see:
» BS / MS with 2+ years of relevant experience
» Strong digital design experience
» Experience in design of complex features or units
» Background in RTL coding using Verilog or System Verilog
» Experience in using design and verification tools (Synthesis, lint, simulation tools)
» Knowledge of industry specifications like CHI/AXI/ACE
» Experience in memory management unit, interconnect design or cache controller design desirable
» Good debugging and problem solving skills. Scripting knowledge
» Good interpersonal skills and ability & desire to work as a team
How to Apply :
All interested and eligible candidates can apply in online mode for Data Design Engineer position.
Join our Telegram group: Click here
Follow us on Instagram: Click here
Join our WhatsApp group: Click here
Data Design Engineer Salary : The salary for this role is upto ₹ 28.00 LPA *
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About NVIDIA
NVIDIA, a leading technology company, revolutionizes visual computing. With their cutting-edge GPUs and AI technologies, they empower industries ranging from gaming to healthcare. Their dedication to innovation has earned them global recognition and numerous awards. Nvidia’s commitment to pushing boundaries continues to shape the future of graphics processing, enabling immersive experiences and advancing artificial intelligence capabilities.
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* – Approximate pay range
